1. Field of the Invention
The present invention generally relates to a structure of a device and a manufacturing method thereof, and in particular, to a pixel structure and a manufacturing method thereof.
2. Description of Related Art
A flat panel display mainly includes the following: an organic electroluminescence display, a plasma display panel and a thin film transistor liquid crystal display, where the thin film transistor liquid crystal display is the most widely used. Generally speaking, the thin film transistor liquid crystal display is mainly formed of a thin film transistor array substrate, a color filter substrate and a liquid crystal layer, where the thin film transistor array substrate includes multiple scan lines, multiple common electrode lines, multiple data lines, multiple active devices arranged in arrays and multiple pixel electrodes connected to the active devices, and each active device having a gate electrode, a source electrode and a drain electrode is electrically connected to the corresponding scan line and data line respectively.
The manufacturing procedure of the thin film transistor array substrate usually includes multiple times of photo-lithography and etching steps. In common manufacturing techniques, the gate electrode, the scan line and the common electrode line are constituted by use of the first conductive layer, the source electrode, the drain electrode and the data line are constituted by use of the second conductive layer, where at least one dielectric layer is disposed between the first conductive layer and the second conductive layer, and the second conductive layer is closer to the pixel electrode than the first conductive layer. Due to the coupling effect between the pixel electrode and the data line, such design usually affects the display voltage of the pixel electrode. Therefore, a technique that the data line is manufactured by using the first conductive layer is provided, and in such technique, the common electrode line is manufactured by only using the second conductive layer, so that the disposition areas of the common electrode line and the data line overlap to reduce the occupied area of the metal conductive components. However, the common electrode line at least partly overlaps with the data line, so that a so-called parasitic capacitance usually exists between the common electrode line and the data line. The existence of the parasitic capacitance will increase the load of the data line, which is unfavourable to the driving of the thin film transistor array.